Invited Speakers

Table of Contents

Invited Talk #1: Mobile Ionic Field Effect Transistors with Amorphous Dielectrics: Device Demonstration and Modeling

Dr. Xiao Yu
Zhejiang Lab, China

Abstract: We have reported ferroelectric (FE)-like behaviors with an amorphous (a-) ZrO2. The physical origin of the FE-like behaviors is systematically investigated by electrical characterization, and confirmed to be the movement of mobile ions existing in the amorphous thin film. A physics-based model for the mobile-ionic field-effect transistor (MIFET) predicts the ferroelectric-type hysteresis and steep subthreshold slope characteristics, which have been demonstrated in an experiment using fabricated MIFET with a-ZrO2 film. Thanks to the modulation of mobile ion, analog synapse based on ZrO2 MIFET exhibits superior symmetry and linearity for both potentiation and depression, has been successfully demonstrated for spiking neural network (SNN) applications. Due to the outstanding property of a-ZrO2, the MIFETs exhibit higher endurance, lower thermal budget, and better scalability than FeFETs with crystallized doped-HfO2, indicating a novel technology for memory and computing applications.

Invited Talk #2: In-memory computing using emerging technologies: opportunities and challenges

Dr. Quang-Kien Trinh
Le Quy Don Technical University

Abstract: In this brief, we introduce a promising Edge-AI computing design based on the binarized spiking neural network using emerging spintronic memory devices. At the circuit level, presynaptic spikes are fed to memory units through differential bit lines (BLs), while binarized weights are stored in a subarray of nonvolatile STT-MRAM. When the common inputs are fed through BLs, vector-to-matrix multiplication can be performed in a single memory sensing phase, hence achieving massive parallelism with low power and low latency. We further proposed IF circuit can mimic both addition and subtraction operations that permit better incorporation with in-memory XNOR-based synapses to implement the BSNN processing core. To evaluate the proposed design, we have developed a framework that incorporates the circuit’s imperfections effects into the system-level simulation. The array circuits use 2T-2J spin-transfer-torque magnetoresistive RAM (STT-MRAM) based on a 65-nm commercial CMOS and a fitted magnetic tunnel junction (MTJ). The system model has been described in Pytorch to best fit the extracted parameters from circuit levels, including the cover of device nonidealities and process variations. The simulation results show that the proposed design can achieve a performance of 5.10 fJ/synapse and reaches 82.01% classification accuracy for CIFAR-10 under process variation.

Invited Talk #3: Beyond 5G: a view from semiconductors materials to systems

Dr. Luis Andia

Abstract: As 5G continues to be deployed worldwide, recent material engineering advances are helping connect an unprecedented number of users – people but also objects and machines. But several technical challenges still need to be addressed in order to take full advantage of 5G’s potential. This presentation will focus on the 5G RF Front Ends implementation challenges and how a collaborative effort of all the ecosystem actors - from engineered materials to application providers – addresses them. This presentation will first introduce the benefits of RF-SOI to the most prominent RFFE semiconductor technologies for 5G FR1 (sub 8GHz). Second, it will discuss how some of the engineered material experience gained in 5G FR1 RFFE implementation could be leveraged into 5G FR2 (mmWave frequencies) and the characteristics of the new technologies needed to address the use of such new frequency bands. Finally, we would explore the path that 6G could take in the mid-term future and its implications on the RFFE semiconductor technologies.

Invited Talk #4: SOI CMOS technologies for RF and millimeter-wave communication systems

Professor Jean Pierre Raskin
Universite Catholique de Louvain, Belgium

Abstract: Radio Frequency (RF) performance of an integrated circuit (IC) does not only depend on the analog and high frequency characteristics of the active devices, i.e. the transistors, but also the quality of the back-end of line (BEOL) process which defines the losses along the interconnection lines and the quality factor of the passive elements such as the inductors and tunable capacitors, as well as the electromagnetic properties of the substrate on which the RF IC is lying. The parasitic resistances (metal lines and vias) and capacitances (dielectric layers) along the interconnection constitute a low-pass filter which drastically limits the operational frequency of ICs [1]. Advanced BEOL process provides higher number of metal lines, thicker metal layers, low-k dielectric interlayers and denser vias using carbon nanotubes are investigated for diminishing the parasitic resistances between metal layers [2, 3]. The substrate losses, crosstalk and non-linearities remain the major challenges for designing high-performance RF ICs in Si-based technologies. The root cause of missing RF performance of high-resistivity (HR) Silicon-on-Insulator (SOI) substrate was found by demonstrating the existence of a parasitic surface conduction [4, 5] below the buried oxide (BOX) and the way to disable it by introducing traps. In 2005, the possibility of creating SOI substrates characterized with an effective resistivity [6] as high as 10 kΩ.cm thanks to the introduction of a thin undoped polysilicon layer below the BOX of a HR SOI substrate was demonstrated [7].

Today, Partially Depleted (PD) SOI transistors with a channel length of 90 or 130 nm combined with a HR trap-rich SOI substrate is the mainstream technology for RF ICs. New generation of mobile communication systems such as 5G and 6G require higher cut-off frequency for the system, better linearity and lower power consumption. Moreover, the integration of high-quality inductors requires higher number and thicker metal layers. To fulfil those requirements, RF SOI must move to shorter nodes. Fully Depleted (FD) electronic regime is a promising approach to continue the scaling down of MOSFETs while controlling the short channel effects (SCE). In order to limit SCE, the channel thickness must be approximately 1/4 and 2/3 of the channel length, respectively, in the case of ultra-thin body and buried oxide (UTBB) and FinFET. Technological aspects, electrostatics, scalability and variability issues in UTBB FD-SOI MOSFETs as well as their perspectives for low power digital applications are widely discussed and shown to be excellent [8, 9].

In this paper, the main interesting features of the FD SOI CMOS technology for RF and millimeter-wave applications are presented. Firstly, the low-power and high-frequency performance of FD SOI [10]-[12] featuring various types of back gate contacts are shown for operation at cryogenic [13] and high temperature [14]. The benefit of the back gate biasing to improve the RF noise characteristics [15] as well as the transistor linearity [16] is demonstrated. Secondly, the importance of moving from standard to high-resistivity Si substrate to reduce the crosstalk issues [17], interconnection RF losses and non-linearities [18] are presented. The non-linear model for the engineered trap-rich SOI substrate is detailed [19, 20], and finally a brief review of SOI ICs in RF and millimeter-wave domain is given [21-24].

Invited Talk #5: Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling

Dr. Anabela Veloso
IMEC, Belgium

Abstract: We report on vertically stacked nanosheet (NS) FETs, focusing on the combined inner spacers and source/drain (S/D) epitaxial growth modules sequence, a key integration flow differentiator as compared to finFETs, addressing the impact and control of parasitics and channel strain engineering. The use of both wafer sides for device connection, via nTSVs landing on buried power rails (BPR) after extreme wafer thinning, is also discussed. This configuration is shown to be advantageous for obtaining reduced IR drop values and for, overall, enabling enhanced performance and additional area scaling. It also has the potential to further expand such as to include extra options, together with novel devices/circuits and for various applications.

Invited Talk #6: Engineered SiC materials for power technologies

Dr. Walter Schwarzenbach

Abstract: SmartSiC(TM) engineered substrates are proposed to answer the power device needs for high quality, ultra low resistivity materials. 150mm substrates demonstrate Smart Cut(TM) technology potentials, opening the path to defect free layers and 200mm substrates.

Invited Talk #7: From resilience to Resistive Memory variability in Binarized Neural Networks to exploitation of variability in Bayesian Neural Network

CEA, France

Abstract: Resistive memory technologies are promising technologies for energy-efficient hardware implementation of intelligent systems that process information locally at the edge. However, current approaches are difficult to implement due to the intrinsic non-idealities of resistive memory. We present on the one hand binarized neural networks that are extremely resilient to errors and which operates at low energy consumption regimes and on the other hand a machine learning scheme that exploits memristor variability to implement Markov chain Monte Carlo sampling configured as a Bayesian machine learning model. Our approaches demonstrates robustness to device variability, degradation, and, based on circuit and systemlevel simulations, the total energy to perform a classification and to train models is estimated to be two order of magnitude lower than in complementary metal–oxide–semiconductor (CMOS)-based approaches.

Invited Talk #8: Memristor-based neuromorphic computing and beyond

Professor Jianshi Tang
Tsinghua University, China

Abstract: In the past decade, the rapid growth of artificial intelligence demands for intelligent computing chips. However, the continuous increase of computing power and energy efficiency for conventional chips face critical challenges from the slowdown of Moore’s law scaling and also their von Neumann architecture. Inspired by human brain, computing-in-memory with emerging devices, such as memristors, has emerged as a promising neuromorphic paradigm to break the von Neumann bottleneck. Tremendous progress has been recently made in the developments of oxide-based memristors as neuromorphic devices, such as artificial synapses, neurons as well as dendrites. In this talk, I will first discuss the hardware challenges for artificial intelligence and then introduce the recent progress on the memristor-based computing-in-memory for neuromorphic computing, from material and device developments to process integration and chip demonstrations. Recent works on memristor-based signal processing for dendritic computing and reservoir computing will also be discussed. As the end, I will highlight future research directions and challenges for memristor-based neuromorphic computing.

Invited Talk #9: Ferroelectric Capacitive Memory for Storage and In-memory Computing

Professor Gong Xiao
National Singapore University, Singapore

Abstract: In the era of big data with data-intensive computing tasks, the search for emerging non-volatile memories (eNVMs) with high data storage density, fast speed, low power consumption, and good reliability is becoming increasingly urgent. In this talk, I am going to present a new concept and solution using capacitive memory based on doped-HfO2 ferroelectric (FE) material with near-zero static power in principle and low read disturbance. I will talk about the experimental demonstration of an inversion-type ferroelectric capacitive memory (FCM) as well as world’s first 1 kbit (32×32) FCM crossbar array on a SOI substrate.

Invited Talk #10: Direct verification of Quasi-Static Negative Capacitance (QSNC) and its applications

Prof. Daewoong Kwon
Inha University, Korea

**Abstract: ** The operating principle of negative capacitance FET (NCFET), which has been spotlighted as a next-generation low-power logic semiconductor device, and the materials and electrical characteristics that NCFETs must have for commercialization, and the demonstrated state-of-art NCFETs, are reviewed and challenges to be overcome are explained. In particular, the possibility of implementing quasi-static negative capacitance (QSNC), which has been considered as one of the critical problems of NCFETs, is explained from the material and device design point of view. The previously reported improvement in the switching performance of ferroelectric-gated FETs using a ferroelectric film as a gate insulator is analyzed from both QSNC and transient polarization switching perspectives, and an essential verification method to verify the QSNC implementation is presented. Also, QSNC direct verification through polarization extraction from the manufactured NCFET is demonstrated and its validity is confirmed. Finally, through the measurements of the electrical characteristics from nanoscale Fin-NCFETs which have a gate insulator stack (including interlayer + ferroelectric film) with an effective oxide film thickness (EOT) of 1 nm or less, the performance improvement that an NCFET implemented with QSNC can have is confirmed, and by utilizing a fabricated SRAM array composed of Fin-NCFETs, the feasibility of low-power content-addressable memory (CAM) and binary neural network (BNN) applications are experimentally verified.

Invited Talk #11: Low power Wake up Receiver for IoT applications

Professor Koichiro Ishibashi
UEC Tokyo

Invited Talk #12: Edge Intelligence for IoT Wearable Sensors

Professor Deepu John
University College Dublin

Abstract: This talk presents a brief overview of popular deep learning techniques and various optimization and model compression strategies for implementing these techniques in low-power, low-cost embedded devices. Further, a lightweight electrocardiogram (ECG) classification neural network for real-time binary classification of ECG beats into Normal or Anomalous beats is presented. The network utilizes an architecture consisting of Long Short-Term Memory (LSTM) cells and Multi-Layer Perceptron (MLP). The LSTM takes in a sequence of coefficients representing ECG signal morphology while the MLP is trained with features derived from instantaneous heart rate.  The network was mapped to a fixed-point model, in a bit accurate fixed-point environment and ported to a Cortex ARM M4 based embedded platform. The overall system was successfully demonstrated with a significant saving of 50% power achieved by gating the wireless transmission.

Invited Talk #13: 140-GHz Energy-Efficient OOK Receiver using Self-Mixer-Based Power Detector in 65nm CMOS

Dr. Nguyen Ngoc Mai Khanh
University of Tokyo

Abstract: This talk presents an integrated 140 GHz receiver in 65nm CMOS including a power detector for high-bandwidth and power-efficient communication and radar applications. The mm-wave power detector ultilizes a self-mixer scheme by the use of an NMOS transistor fed to a simple RC low-pass filter. Measured result shows that it can operate in a wide-band frequency range of 134–158 GHz and the proposed receiver occupies a small core area of 220umx220um. To realize the demodulated waveform and bit error rate (BER) measurements, we fabricated a prototype including an OOK modulator followed by the proposed receiver in a 65nm CMOS process. The prototype successfully demonstrates a demodulated waveform and BER test at 11Gb/s with a carrier frequency of 140 GHz. The measured BER is 2.1x10−4 at 11Gb/s and less than 10−11, which is a limit of the BERT, at 8Gb/s or less. Our OOK transceiver prototype can achieve low power, high isolation, and small die area with more design freedom and suitable for mm-wave D-band communication or radar systems.

Invited Talk #14: Configurable Intelligent Power management IC Solutions

Harry Trinh

Abstract: We use power on a minute-by-minute basis. Power is money the more you spend the more it costs. Power is comfort, you loose access to it like running out of battery on your phone or your hearing aid there goes the comfort. This presentation is about how we can better manage power usage in systems and how the built-in intelligence and configurability in power management devices helps us control, monitor optimize and manage the power distribution and conversion in a system to enhance size, weight and cost which are today electronic device design challenges.

Invited Talk #15: Novel Tunnel- and Ferroelectric-based Devices by Mechanism Engineering for Ultra-Low Power Applications

Dr. Huang Qianqian
Peking University, China

Abstract: Power dissipation is one of the most critical issues for nanoelectronic circuits. For low-power logic applications, Tunnel FET (TFET) and ferroelectric (FE) based negative-capacitance FET (NCFET) can break the fundamental limitation of subthreshold swing in conventional MOSFET. In this talk, from the perspective of mechanism engineering, a new kind of steep-slope device with hybrid operation mechanism is presented with the state-of-the-art comprehensive electric properties, fundamentally addressing the issue of low drive current in conventional TFETs [1-3]. Furthermore, a novel energy-efficient TFET-CMOS hybrid foundry platform based on 300nm CMOS baseline process is also demonstrated for power-constraint AIoT applications [4-5]. For FE-HfO2-based NCFET devices, the possibility of NCFET as a steep-slope device for high-speed and low-voltage operation will be re-assessed based on our proposed dynamic negative capacitance theory [6-7]. Besides, by exploiting the inherent physics of FE polarization switching, this talk will present that ferroelectric-based devices can be utilized for ultralow hardware-cost and high energy-efficient solutions for emerging computing applications. As an example, by utilizing the non-volatile polarization switching dynamics and three-terminal structure of hafnia-based FeFET device, we propose novel Leaky-FeFET based designs to mimic biological neurons [8-9], and a novel FeFET-based time-domain computing in memory system with the record highest area and energy efficiency [10]. By combing the features of FE layer with TFET device, a novel ferroelectric TFET (FeTFET) based content addressable memory cell with only one transistor is proposed and experimentally demonstrated [11], showing its great potential for area- and energy-efficient machine learning applications.

Invited Talk #16: 3-Dimensional Integration with High Interconnection Density

Professor Rino Choi
Inha University, Korea

Abstract: A conventional 2-dimensional scaling down seems to reach its fundamental limits. Further increasing areal integration density required a significant investment of time and money as the dimension of the devices becomes close to those of molecules. On the other hand, the systems that has been requested lately should require more functions to be incorporated in a constrained space. Therefore, 3-dimensional stacking of device layers has attracted attention. To take over 2D scaling of system-on-chip approach, 3D integration should have high density of interconnection density. In this talk, 3D integration for high interconnect density technologies would be addressed. Monolithic 3D is a sequential 3D integration technique to stack multiple device that was proposed to increase integration density and decrease the signal delay and power consumption by reducing interconnection length. Hybrid bonding is a parallel 3D integration technique having a dielectric bond with embedded metal to form interconnections. Higher connectivity can be accomplished because solder bumps on dies are not required to make connections. However, to adopt these technologies, it is necessary to develop novel process techniques and study several technical issues.

Invited Talk #17: Smart Cut Technology: From Substrate Engineering to Advanced 3D Integration

Dr. Guillaume Besnard

Abstract: In this paper, we revisit how Smart Cut has played a major role to fabricated innovative substrates and how it can further enable heterogeneous integration for upcoming 2.5D/3D technologies. We demonstrate the unlimited possibilities of thin layer transfer, materials and stacking engineering to achieve best performance, energy efficient and cost-effective IC solutions for mobile communication, automotive and AIoT applications. All the learnings done and to come in substrate manufacturing will help the future of stacking at nanometer scale as we show first research implementation of the process into a CMOS flow.

Invited Talk #18: Monolithic 3D III-V HEMT for future communication and quantum computing

Dr. Sanghyeon Kim
KAIST, Korea

Abstract: Recently, monolithic 3-dimensional (M3D) integration has stirred much attention in various applications such as CMOS, RF, image sensors, etc. In terms of the materials, III-V could be promising candidates due to their superior material characteristics and low process temperature, which are important constrain in M3D integration. In this talk, we discuss one of the potential applications of III-V-based M3D including communication and quantum computing.

Invited Talk #19: Enablement of CMOS integrated sensor, harvesting and storage applications by ferroelectric HfO2

Dr. Wenke Weinreich
Fraunhofer Institute, Dresden, Germany

Abstract: The CMOS compatible material hafnium dioxide shows the ferroelectric effect if deposited as thin film and stabilized in the orthorhombic phase. Next to the scaling potential of ferroelectric memories like FRAM or FeFET, the inherent pyroelectric and piezoelectric properties can be addressed. Indeed, both effects are proven in HfO2 thin films and the according coefficients surpass further CMOS compatible materials and partially reach the high values of common non-CMOS materials like PZT. By that, silicon integration of miniaturized sensors, energy harvesters and energy storage is possible and the current status of developing such applications is reviewed in this paper.

Invited Talk #20: Device engineering guidelines for performance boost in IGZO front gated TFTs based on defect control

Dr. Subhali Subhechha

Abstract: Defect control in IGZO-TFTs strongly impacts the device performance. Here, different device design guidelines for performance boost are discussed, including device architecture, integration schemes, stack engineering for defect control in order to boost the device performance.

Invited Talk #21: GaN-on-Si microwave and mm-Wave devices

Prof. Zhihong Liu
Xidian University, China

Abstract: During the last two decades, gallium nitride (GaN) based materials have emerged and demonstrated strong competitiveness in the fields of RF applications. Benefitted from the unique material properties such as wide-band gap, high critical electrical field, strong spontaneous and piezoelectric polarization, and high saturation velocity etc., GaN microwave and mm-wave transistors exhibit excellent performance including high output power, high efficiency, high temperature operation ability etc.. GaN grown a Si substrate, so called GaN-on-Si, holds the combination of the advantages from GaN and the Si substrate such as low cost, large wafer availability, and mass-production possibility using the mature Si foundries. In this talk we would like to give a brief overview on our progress of the research and development of GaN-on-Si microwave and mm-wave devices, including GaN-on-Si high electron mobility transistors (HEMTs), monolithic microwave integrated circuits (MMICs) for high-voltage power amplifier (PA) applications, low noise amplifier (LNA) applications, and low-voltage mobile SoC applications. The efforts to realize CMOS-compatible fabrication for GaN devices and GaN RF-Si CMOS heterogeneous integration will also be introduced. Finally, the future opportunities of GaN-on-Si device technologies and the relative challenges will be predicted.

Invited Talk #22: High performace RF devices in an advanced FDSOI process enabling integrated Watt-level power amplifiers for WiFi applications

Dr. Viet Thanh Dinh
NXP Semiconductor, USA

Abstract: Wireless connectivity is the key enabler for Internet of Things. Cost-effective high-performance RF front-end ICs are needed to facilitate RF connections from low power (BLE / Zigbee, 2.4GHz) to high power (WiFi 6E, 5-7GHz). For the transmitter part (TX), these RF systems consist of integrated power amplifiers (PA), which must deliver enough power (up to 1W) with good linearity and high efficiency. This paper reviews critical high-voltage RF active and passive devices which are required to design such an integrated RF power amplifier at Watt-level including LDMOS, fringe capacitors, transformers and inductors. A 3.3V / 5V RF-LDMOS with a cutoff frequency beyond 100GHz, designed and fabricated without any additional dedicated mask in an advanced sub-28nm node FDSOI process, is reported. For passive devices, by combining the novel RF design with an RF-compatible metal stack, accurate EM simulation and 4-port RF characterization, a record high Q-factor for a 7V-fringe capacitor, a 2-way transformer and 8-shaped inductors are obtained. The RF performance of these high-voltage (HV) capable devices is comparable to best-in-class devices in RF-HV-centric non-CMOS processes, which enables highly integrated cost-effective power amplifiers for WiFi applications and beyond.

Invited Talk #23: 3-levels-stacked InxGa1-xAs Multi-Bridge Channel Field-Effect-Transistors

Dr. In-Geun Lee
Kyungpook National University, Korea

Abstract: The gate-all-around (GAA) multi-bridge channel FET (MBCFET) architecture is believed to be the final evolutionary step for Moore’s law. To achieve a sufficient amount of ION at low VDD, it would be essential to use high-mobility channel materials including III-Vs and Ge. In particular, indium-rich InxGa1-xAs material systems with x in excess of 0.53 are regarded as a promising channel material for future CMOS logic and memory applications due to their exceptional electron carrier transport properties, including a very high injection velocity (vinj). In this talk, we present 3-levels-stacked In0.53Ga0.47As GAA MBCFETs with selectively regrown n+ In0.53Ga0.47As source/drain contacts by MOCVD. For a device fabrication, we use an epitaxy wafer with an In0.53Ga0.47As/In0.52Al0.48As multi-superlattice structure, and vertically stacked channels are electrically connected to selectively regrown n+ In0.53Ga0.47As contacts in the source/drain region. In0.52Al0.48As sacrificial layers are etched isotropically with an HCl-based etchant, releasing the In0.53Ga0.47As nanosheet (NS) channel layers. The device adopts an ALD-grown high-k dielectric layer of HfO2 and a TiN metal gate to implement the GAA structure. The fabricated MBCFETs with Lg = 130 nm, WNS = 300 nm and tNS = 15 nm exhibit a combination of ION = 2.2 mA/m and gm_max = 5.7 mS/m at VDS = 0.8 V, making efficient use of each multi-bridge channel along the S/D and gate width directions.

Invited Talk #24: InGaAs HEMTs and Their Integration with Si CMOS for energy efficient hybrid circuits: Exploring the path for future wireless communication

Dr. Annie Kumar
National University of Singapore, Singapore

Abstract: Integration of InGaAs HEMTs and Si CMOS on large area silicon substrates holds great promise to cater to the needs of beyond 5G technologies owing to the extremely high electron mobility and bandgap engineering of InGaAs material systems and the mature Si platform. We discuss the hybrid integration platform, where InGaAs HEMT layers grown on 200 mm Si substrate are bonded with Si-CMOS wafers using a multi-layer transfer method. Furthermore, to enable the integration of InGaAs HEMTs and Si CMOS on the same Si substrate, we demonstrate high performance InGaAs Schottky HEMTs on the 200 mm Si substrate and assess the suitability of InGaAs HEMT devices for BEOL processing temperatures.