Tutorial #1: RISC-V Computer System Designed for Cyber-Security

Trong-Thuc Hoang1, Ba-Anh Dao2, Anh-Tien Le1,2, Van-Phuc Hoang3 and Cong-Kha Pham1
1University of Electro-Communications (UEC), Tokyo, Japan
2Academy of Cryptography Techniques (ACT), Hanoi, Vietnam
3Le Quy Don Technical University (LQDTU), Hanoi, Vietnam

The problem with cyber-security is always the up-to-date issue. There will be no final solution to prevent all hacks, as no perfect attack model could break all the systems. The fight between attacker and protector is an everlasting game. Therefore, it is not how sharp the weapon is, but the ability to adapt that will be the key to preventing us from an uphill battle. With a highly customizable architecture and a solid open-source community, RISC-V is the opportunity for hardware developers to gain the upper hand in security, especially in Side-Channel Attacks (SCAs). This talk describes designing a secure computer system using the RISC-V architecture.

For traditional adversaries like malware or viruses that exploit bugs in an Operating System (OS), a robust Trusted Execution Environment (TEE) is the solution. The design philosophy of TEE is to set up a trusted domain that is wholly separated from the conventional Rich Execution Environment (REE) such as Linux and Windows. Therefore, any unauthenticated code cannot operate on the trusted side. This isolation is done by a barrier between programs using privilege separation. To do that, TEE has to set up a Chain-of-Trust (CoT), a series of authentication processes between layers in the OS stack. The beginning of CoT is the Root-of-Trust (RoT), the very first authentication of the system at reset. For security reasons, RoT should be inaccessible by the REE or even the TEE processors after boot. Therefore, the first example in this talk is designing a system that can provide a flexible and secure boot procedure with RoT isolated from the TEE processors.

However, even with TEE and isolated RoT, the computer system is still subjected to SCAs. The next part of this talk gives two examples of SCAs, one with software and one with hardware approaches. For software-based SCA, the concept of Micro-Architectural Analysis (MAA) could exploit the processor’s states in a cryptographic system, allowing an attacker to take advantage of the executed program. In 2018, Spectre was revealed as a severe security flaw with a practical example of an MAA attack. It exploits speculative execution in Out-of-Order (OoO) processors to retrieve data through caches. This example has successfully replicated the Spectre attack to illustrate the vulnerability of OoO RISC-V processors. This cache-based SCA can be studied and mitigated by implementing a small hardware adjustment inside the Miss Status Holding Register (MSHR).

For hardware-based SCA, the most renowned attack is the Correlation Power Analysis (CPA) attack. An attacker could obtain the secret key when the targeted device performs cryptographic functions by collecting and analyzing its power consumption or electromagnetic radiation traces. Therefore, the final part of this talk shows a design example to prevent CPA attacks using Random Dynamic Frequency Scaling (RDFS). In this example, a RISC-V System-on-Chip (SoC) is integrated with a cryptographic accelerator. Only the operating clock frequency of the crypto-core is dynamically scaled after each encryption/decryption to create severe misalignments in the targeted SoC’s power traces. The RDFS technique helps improve the CPA resistance while maintaining the architecture’s low-performance overhead and hardware costs. The effectiveness is demonstrated by conducting realistic CPA attacks, deep-Learning-based SCA, and Test Vector Leakage Assessment (TVLA) testing.

Tutorial #2: Marriage of Ferroelectric Memories and BEOL-compatible Oxide Semiconductors to Empower Future Integrated Circuits

Dr. Gong Xiao
National University of Singapore

Abstract: In this talk, I will present our recent research progress on HfO2-based ferroelectric memories and monolithic 3D integration enabled by oxide semiconductor transistors for future integrated circuits. I will start with the motivation for emerging non-volatile memories and monolithic 3D integration. This will be followed by introducing various doped-HfO2 ferroelectric materials and two types of ferroelectric memories, i.e. FeFET and FTJ. I will then move on to discuss how to use these ferroelectric memories for in-memory computing as well as how to integrate these memories in a 3D monolithic manner by using oxide semiconductors to explore their full potential. The talk will end with a summary and adoption challenges.

Bibliography: Dr. Gong Xiao is currently an Assistant Professor in the ECE Department of the National University of Singapore (NUS). He obtained his Ph. D Degree from NUS and was a Visiting Scientist at MIT in the year of 2014. His research interest includes advanced transistors and emerging memories for in-memory computing, ultra-high frequency and ultra-wide bandgap device technology, monolithic 3D integration, as well as opto-electronic integrated circuits and their applications in quantum technology. He has more than 200 publications in international journals and conferences, including 49 papers in IEDM and VLSI Symposium. He has won many awards, including the Bronze Medal at the 6th TSMC Outstanding Student Researcher Award, Emerging Leaders in Journal of Physics D: Applied Physics, Best Student Paper Award at VLSI Symposium, the Best Demo Paper Award at VLSI Symposium, the Best Paper Award at ICICDT, and NUS Engineering Teaching Commendation Award. His work has been reported by various high-profile magazines such as IEEE Spectrum, Compound Semiconductors, and Semiconductor Today. He is the Technical Program Chair or the member of TPC for many conferences, such as ICICDT, EDTM, IEDM, VLSI-TSA, ECS , IWJT, etc.

Tutorial #3: State-of-the-Art Techniques for Hardware Security - From Design Methodologies to On-Chip Intelligent Sensors

Prof. Massimo Alioto, Ph.D.
ECE - National University of Singapore
E-mail: massimo.alioto@nus.edu.sg, malioto@ieee.org

Abstract: This decade is witnessing substantially heightened threats to the security of hardware systems, and systems on chip in particular. On one hand, the attack surface is growing exponentially like the number of connected devices, which is running towards the trillion scale. On the other hand, conventional hardware security techniques prove very expensive for the vast majority of devices, needing innovation to lower cost and power to fit the budget of low-end devices. At the same time, physical attacks are becoming inexpensive and widely accessible to adversaries, requiring low-cost always-on sensors for attack detection and counteraction.

This tutorial provides a broad picture of the key challenges posed by the scale-up to the trillion scale, and a clear understanding of the technological trends in the key components of secure systems. Then, a reasoned overview is provided on state-of-the-art design methodologies to embed security primitives into logic and memory fabrics at low cost and power, overcoming the security shortcomings of conventional design partitioning. Fully-automated design techniques enabling physical awareness are then discussed from non-invasive to invasive attacks, along with intelligent on-chip sensing techniques for attack detection. Counteraction techniques including new machine learning-based solutions for hardware patching are finally discussed to deal with the ever-changing threat landscape.

In this tutorial, several silicon demonstrations are introduced as case studies to illustrate the benefits and the limits of existing hardware security frameworks, and to identify challenges and opportunities for the decade ahead. The tutorial is accompanied by a public database constantly maintained by our Green IC group, which enables the attendees to remain up-to-date and understand the security landscape well after the conference.

Biography: Massimo Alioto (M’01–SM’07-F’16) received the MSc degree in Electronics Engineering and the Ph.D. degree in Electrical Engineering from the University of Catania (Italy) in 1997 and 2001. He is currently a Professor at the Department of Electrical and Computer Engineering, National University of Singapore, where he leads the Green IC group, and is the Director of the Integrated Circuits and Embedded Systems area, and the FD-FAbrICS research center at NUS. Previously, he held positions at the University of Siena, Intel Labs – CRL (2013), University of Michigan Ann Arbor (2011-2012), BWRC – University of California, Berkeley (2009-2011), and EPFL (Switzerland, 2007). He has authored or co-authored about 350 publications on journals and conference proceedings. He is author of six books, including Enabling the Internet of Things - from Circuits to Systems (Springer, 2017). His primary research interests include self-powered wireless integrated systems, widely energy-scalable integrated systems, data-driven silicon systems, hardware security from circuit to sensing, and emerging technologies, among the others.

He is the Editor in Chief of the IEEE Transactions on VLSI Systems, and was the Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems. He is/was Distinguished Lecturer of the IEEE Solid-State Circuits Society and the IEEE Circuits and Systems Society, for which he is/was also member of the Board of Governors and Chair of the “VLSI Systems and Applications” Technical Committee. He served as Guest Editor of several IEEE journal special issues, and Associate Editor of a number of IEEE and ACM journals. He is/was Technical Program Chair and Track Chair in a number of IEEE conferences (e.g., ISCAS 2023, SOCC, ICECS), and is currently in the IEEE “Digital architectures and systems” ISSCC subcommittee, and the ASSCC TPC. Prof. Alioto is an IEEE Fellow.

Tutorial #4: Smart CutTM: Engineered substrate for device performance enhancement

Dr. Walter Schwarzenbach
Soitec, France

Abstract: For decades, Smart CutTM technology has offered a wide range of engineered substrates produced in high volume manufacturing. It opened a large product portfolio, including numerous silicon on insulator (SOI) generations, allowing 2.5D/3D device integration and opening the path to enhanced silicon carbide materials. In this talk, we will review the main features of the Smart CutTM process, and focus on some of the specificities attached to its applications. Among other examples, we will consider the atomic layer thickness control allowing fully-depleted device ultra-low variability, or the new ultra-highly conductive SmartSICTM materials.

Biography: Walter Schwarzenbach (m) has received an Engineer Degree in Physics from the Swiss Federal Institute of Technology in Lausanne in 1994, and a PhD Degree in Physics from the University of Grenoble in 1999. He joined Soitec in 2000 as process development engineer then became project leader in charge of Smart CutTM process industrialization for several 300mm Partially-Depleted SOI substrate generations. From 2009 to 2018, he was in charge as Product Leader of Fully-Depleted SOI, Imager SOI and 2.5D - 3D materials definition and introduction. Since 2019, as part of the Innovation team, he is Technology Manager for SmartCut SiC engineered substrates, said Smart CutTM. He is author or co-author of more than 50 articles in international refereed journals and conferences and more than 30 patents.

Tutorial #5: Agile IC design for Energy-Efficient Sensor Nodes for the Internet of Things

Dr. Orazio Aiello
University of Genova, Italy

Abstract: The Internet of Thing Era enables a world with pervasive and interconnected integrated electronic systems embedded in everyday life objects that collect, process, and exchange useful information for distributed sensing and data acquisition. Energy-autonomous and low-cost systems demand a small area, low design effort, digital-like shrinkage across CMOS generations, and design/technology portability. The possibility to exploit the digital (automated) design flow even for analog building blocks can dramatically reduce the design effort of any system-on-chip that faces the analog signal. Since data processing is digital, but most signals from the real world are analog, almost any electronic device that interfaces with the surrounding environment will benefit from the outcomes of this investigation. In this framework, the tutorial illustrates the concepts and the design flows which enable the implementation of analog functions by true digital circuits.

Biography: Orazio Aiello (Senior Member, IEEE) received the BSc and MSc degrees (cum laude) from the University of Catania, Italy, in 2005 and 2008, respectively, and the M.Sc. degree (cum laude) from the Scuola Superiore di Catania, Italy, in 2009. He got the Ph.D. degree from the Politecnico di Torino, Italy, in 2013 where he also was a Research Fellow in a joint project with FIAT-Chrysler Automobiles, Turin. He was a Visiting Ph.D. at Monash University, Melbourne, Australia in 2013 and a Visiting Fellow with the University of Sydney and the University of New South Wales, Sydney, Australia in 2015 and 2016. He was a Mixed Signal IC Designer and an EMC Consultant for STMicroelectronics, Castelletto, Italy (2008 to 2009) and for NXP-Semiconductors, Nijmegen, The Netherlands (2014). Since 2015, he has been working with the Green IC Group at the National University of Singapore, where he has also been a Marie Skłodowska-Curie Individual and a Global Fellow. He is now an Assistant Professor at the University of Genova, Italy. His main research interests include energy-efficient analog-mixed signal circuits and sensor interfaces. Dr Aiello is a member of the IEEE CASS Microlearning AdHoc Committee and is/was a Technical Program Committee Member of a number of conferences, such as NORCAS and APCCAS.